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All compatible upgrades. No results found for the selected filters. Previous Next. The processor is coupled to a scratch pad memory However, if the slave memory controller integrated circuit is an instance of the slave memory controller without a processor coupled thereto, the slave memory controller integrated circuit A may be simplified to exclude the microprocessor interface , the arbiter , and the collision detector The slave memory controller integrated circuit B includes elements of the slave memory controller integrated circuit A and further includes the processor and scratch pad memory integrated in the same die and coupled together as shown.
Otherwise the description and function of the common elements herein is applicable to both the slave memory controller integrated circuit B and the slave memory controller integrated circuit A.
In an alternate embodiment of the invention, the slave memory controller integrated circuit includes elements of the slave memory controller integrated circuit A and further includes the processor integrated in the same die but with an external scratch pad memory. The slave memory controller integrated circuit A interfaces to the one or more memory integrated circuits A- H by the data bus D, the address bus A, one or more chip enable signals E, and one or more control signals C e.
As mentioned previously, the slave memory controller integrated circuit A may adapt to the different access characteristics of various types of IC memory devices used as the one or more memory integrated circuits A- H. The block move engine can adapt to different read and write access times if different types of IC memory devices are used as the one or more memory integrated circuits A- H.
The slave memory controller A interfaces to the master memory controller by the data bus coupled to the edge connector by PCB traces. The shared memory is a random access memory to provide temporary storage of data in a shared memory region. It may be a volatile type of memory and may be referred to herein as a volatile random access memory VRAM.
By way of the block move engine , the shared memory allows both the processor and the master memory controller to access the memory A- H coupled to the slave memory controller in a given memory slice. Thus, if the block move engine is accessing the shared memory, the processor interface may need to wait for the access to the shared memory to complete. Moreover, the processor and the block move engine may try to access the shared memory at the same time resulting in a collision.
The collision detection logic is coupled to the arbiter The collision detection logic is also coupled to the address controller see FIG. The collision detection logic is coupled to the processor interface to monitor the addresses from the processor into the shared memory If there is a concurrent address overlap into the shared memory , the collision detection logic may signal the arbiter to step in and control access to the shared memory If there are concurrent operations by both of the microprocessor and the master memory controller see FIG.
The arbiter signals to the block move engine or the processor through the interface as to which has priority and which has to wait. The arbiter may give preference to the block move engine if the overlapping request for access to the shared memory or the memory A- H occurs at substantially the same time. The first bus multiplexer and the second bus multiplexer are provided to improve the data bandwidth into and out of the block move engine The bit width Y into and out of the block move engine may differ from the bit width X of the data bus to the edge connector and the bit width Z of the data bus D to the memory integrated circuits A- H.
For example, the bit width X may be eight 8 bits, the bit width Y may be sixteen 16 bits, and the bit width Z may be thirty-two 32 bits for each memory slice in one embodiment of the invention. Data from the master memory controller provided on the bus may be directly written into memory A- H through the bus multiplexers - and the block move engine The block size that may be loaded into memory may vary over a range of sizes.
For example, the block size may be as small as 32 bits or as large as eight kilobytes KB in one embodiment of the invention. With a smaller block size, the block move engine may be bypassed by the bus multiplexer selecting data bus instead of data bus such that bus multiplexers - are directly coupled together in a bypass access mode.
Later, the block move engine may read the shared memory and write the data into the memory A- H through the bus multiplexer Alternatively, data in the shared memory may be read and then written into the memory A- H through the bus multiplexer bypassing the block move engine Likewise, data from the memory A- H may be directly read out to the master memory controller through the bus multiplexers - bypassing the block move engine in response to smaller data block sizes or with the assistance of the block move engine in response to larger data block sizes.
Alternatively, data from the memory A- H may be read out into the shared memory through the bus multiplexer and the block move engine or through the bus multiplexer bypassing the block move engine While the master memory controller may access the shared memory and the memory devices A- H in each memory slice in various ways, each microprocessor may also access the shared memory and the memory devices A- H in each memory slice of a respective 2D memory module in various ways.
The microprocessor may write data onto the data bus through the variable latency microprocessor interface The data on the data bus may be selectively written into the memory devices A- H through the block move engine and bus multiplexer or directly through the bus multiplexer bypassing the block move engine The data on the data bus from the microprocessor may also be selectively written into the shared memory for later processing by the block move engine into the memory devices A- H through the block move engine and bus multiplexer Alternatively, data written onto the data bus through the variable latency microprocessor interface by the microprocessor may be read out by the master memory controller through the bus multiplexer The master memory controller may also read memory locations in the shared memory where the microprocessor previously stored data.
In this manner, the microprocessor may communicate with the master memory controller. Data on the data bus may also be read by the microprocessor through the variable latency microprocessor interface Data may be read out from the memory devices A- H onto the data bus through the block move engine and bus multiplexer or directly through the bus multiplexer bypassing the block move engine Data stored in the shared memory , such as by the master memory controller for example, may also be read out onto the data bus for reading by the microprocessor Data written onto the data bus through the bus multiplexer by the master memory controller may also be read by the microprocessor In this manner, the master memory controller may communicate with the microprocessor The microprocessor may store the data into the scratch pad memory where it may be processed.
For those memory modules and ranks selectively activated by the select bits, the address is received by their respective address controllers see FIGS. Referring now momentarily to FIG. The mask bits may be used to set the address range over which the given memory A- H is accessible.
The mask bits alias the address bits into a larger address space. In one configuration, the mask bits may be 8 bits and the address bits may be 16 bits. There may be one mask bit for each memory slice in a two-dimensional memory array.
A second mechanism may be used to selectively activate memory slices and decide whether or not memory slices participate in memory transactions in the two-dimensional array. The bits in the mask register may be used until the bits in the mask register are reset e. The use of the mask register to control memory slice addressing is now described.
The master memory controller initially performs a write operation into the control space of each slave memory controller to set each mask register on each memory module. To mask the write of the mask register itself, the address-level mask bits are used. The mask register includes one or more bits referred to as address range bits representing one or more address ranges that may be supported by the slave memory controller.
When an address range bit is set, the slave memory controller performs the operations in that address range. If an address range bit is not set, the slave memory controller does not perform operations in that address range.
The master memory controller may alter the settings of the address range bits in the mask register Thereafter the new settings of the address range bits govern future operations of the slave memory controller. The logical address is a linear address range.
A number of physical addresses may be skipped for various reasons, such as a bad memory block. For example in FIG. While a memory slice on a 2D memory module may have a number of physical blocks, the number of logical blocks that are accessible may be less. The address register may be used to store a starting address for a sequence of addresses generated by the remapper The address register may be particularly useful for a burst access mode by the master memory controller.
In this case, the address register or the remapper may include a loadable counter that initially stores the starting address and automatically increments the starting address to generate new addresses to selectively access one or more locations in the memory over a plurality of cycles to access blocks of data for a data burst in the burst access mode.
The next operations register may also contain one or more logical addresses that can be coupled into the address remapper for gaining access to the memory A- H. Generally, the next operations register stores the next operation that is to occur with the master memory controller. The insight into the next operation may assist in setting up the next sequence of operations within the slave memory controller, including the next logical address into memory.
Other functional blocks in the slave memory controller A may internally communicate address and control information between them by tri-stating the buffer As discussed previously, the master memory controller may be a pre-existing memory controller updated with a master memory controller software driver to include aspects and functionality of the master memory controller described herein.
Alternatively, the master memory controller may be a new hardware design. The master memory controller may be plugged into a socket or be integrated into a microprocessor as an integrated master memory controller and plugged into a processor socket. The master memory controller may initiate various types of memory accesses in a two-dimensional memory array including a memory access transaction and a memory access operation.
A memory access transaction is a logical memory access into the two-dimensional memory array that is initiated by the master memory controller; A memory access operation is a physical memory access into the two-dimensional memory array that is initiated by the master memory controller. A memory access transaction may involve one or more memory access operations.
For example, a memory access operation may transfer 32 bits of data from each memory slice, while a memory access transaction may transfer an arbitrary size of data within a range, such as from 4 bytes 32 bits to 2 kilo-bytes.
The master memory controller may be an instance of the master memory controller illustrated in FIG. The memory slice interface couples to and between the two-dimensional transpositional buffer and the two-dimensional memory array , such as by buses A- M illustrated in FIG.
The two-dimensional transpositional buffer is a two port buffer memory with different access over each port. The memory slice interface accesses data in the two-dimensional transpositional buffer on a row by row basis. In contrast, the processor interface accesses data in the two-dimensional transpositional buffer on a column by column basis.
In this manner, the access to data may be transposed. That is, the memory slice interface may write data into the two-dimensional transpositional buffer row by row while the processor interface may read out data column by column from the two-dimensional transpositional buffer Similarly, the processor interface may write data into the two-dimensional transpositional buffer column by column while the memory slice interface may read data out of the two-dimensional transpositional buffer row by row.
Data that is written into and read from the two-dimensional transpositional buffer is blocked into data blocks. A data block is a sequence of data bytes having a block size or length. The block size or block length of the data blocks may vary over a range of sizes. The size of the two-dimensional transpositional buffer is variable as well in accordance with the block length or block size of the data blocks.
A request directed to a rank of memory within a two-dimensional memory module may be referred to herein as a compound memory request or a memory module request. A compound memory request is formed of block requests for individual memory slices within a given rank. A block request may also be referred to herein as a memory slice request. If the compound memory request is a read operation, the memory slice data packed together by the memory module in response to the compound memory request may be referred to herein as a compound memory response or a memory module response.
The data retrieved from a memory slice in response to the block request may be referred to herein as a block response or a memory slice response.
A block request is a request for a block size or block length of data. Accordingly, the block size may vary over a range, such as from bytes to 2 kilo-bytes of information for accesses into read-writable non-volatile memory using NAND-gate EEPROM memory devices, from 32 bytes to 2 kilo-bytes of information for access into read-writable non-volatile memory using NOR-gate EEPROM memory devices, or from 4 bytes to 2 kilo-bytes of information for access into the shared memory in the slave memory controller for the respective memory slice of the memory module.
The transposition buffer needs to have space to store all of the data for at least one compound request. The memory space to store the data for one compound request is the resultant product of multiplying the block size and the number of memory slices in a rank together. The number of memory slices within a memory module may be 16 slices per rank, for example.
If implemented in hardware, the size of the two-dimensional transpositional buffer is designed for the maximum block size expected in the range.
If smaller data block sizes are to be used, the buffer controller adapts the addressing of the larger two-dimensional transpositional buffer to the smaller block sizes. If implemented in software, the storage table making up the two-dimensional transpositional buffer is merely redefined for the smaller or larger block sizes.
The height of each column of the two-dimensional transpositional buffer is at least a block size long. The row size may vary over a range as well, such as bits 16 Bytes or bits 64 Bytes , depending upon the type of memory module and the memory slice operations supported into the two dimensional memory array. The structure and function of the master memory controller allows a main or system processor e. The transposition of memory access provided by the master memory controller efficiently uses the available data bandwidth on each memory channel e.
The memory slice interface includes an address encoder to encode addresses for read or write access to one or more memory slices of the 2D memory array. As access into the 2D memory array is over a plurality of memory slices, a plurality of traditional memory requests are aggregated together to access the 2D memory array. A plurality of memory requests are coupled into the request aggregator where they are aggregated together into one or more compound memory requests over one or more memory slices in the 2D memory array.
The compound memory requests including one or more addresses are coupled into the memory slice interface The memory slice interface encodes the addresses with the address encoder and issues the compound memory request into the 2D memory array over one or more of the memory slices MS1-MSZ. If it is a write compound memory request, the memory slice interface may read data out of the two-dimensional transpositional buffer row by row and write it into the 2D memory array.
If it is a read compound memory request, a compound memory response including a concurrent response from every memory slice in the 2D memory array is expected by the master memory controller, even if the memory slice response is only a default known null data response providing a data fill marker for a given memory slice. The known null data response is provided when a memory slice is not active as it was not accessed by the compound memory request. The request aggregator is coupled to the pending operations table to indicate that it is ready to issue a compound memory request.
The pending operations table adds the compound memory requests into its table of row entries that are issued into the 2D main memory. The pending operations table includes table entries each of which include the compound memory request and a tag. The tag may be the memory rank of memory to which the compound memory request is to be issued, if one compound memory request is permitted per rank. Otherwise, the tag may be a unique number assigned to the given compound memory request.
The tag may optionally be appended to the compound memory request and issued into the 2D main memory. In this manner, the pending operations table keeps an accounting of the status of the outstanding compound memory requests so that available data bandwidth in the memory channels of the 2D main memory is efficiently utilized.
As mentioned previously, the memory channels in a 2D main memory may be heterogeneous memory channels having different types of 2D memory modules.
In this case, the master memory controller may be a heterogeneous master memory controller to support the different types of 2D memory modules in each memory channel. Each of these operations may be performed in software, hardware, or a combination thereof. Read requests may be queued together in a read request queue and write requests may be queued together in a write request queue.
The block memory requests are aggregated together into compound memory requests into the two-dimensional memory array by a request aggregator implemented in hardware, software, or a combination thereof to maximize bandwidth over the memory channels therein. For example, the block memory requests Q, Q, and Q may be aggregated together into one read compound memory request into the two-dimensional memory array The compound memory request includes an encoded address that is encoded by an address encoder The compound memory request may optionally include a tag appended by the pending operations table to indicate what pending operation is taking place in the two dimensional memory array for the give compound memory request.
Otherwise, the master memory controller may limit access to the two dimensional memory to one compound memory request per rank and a tag need not be used as the master memory controller knows the expected timing of a compound memory response. The encoded address in the compound memory request is received by one or more slave memory controllers at the slave memory control level to selectively activate one or more memory slices to perform memory operations.
In response to the encoded address, selected memory in each memory slice may be activated on the various memory modules in the two-dimensional memory array For example, consider the compound memory request aggregating the block memory requests Q, Q, and Q.
The compound memory request may concurrently access different memory modules in the memory array within the same rank of memory. For example, the block memory request Q may respectively access a first memory module and a first rank of memory in a second memory slice MS2 to read a first memory block MB 1. The block memory request Q may respectively access a different memory module and its first rank of memory in a fifth memory slice MS5 to read a fifth memory block MB5. The block memory request Q may respectively access a different memory module and its first rank of memory in a fourth memory slice MS4 to read a ninth memory block MB9.
A memory module may have a bad block of memory and be unable to use one or blocks of memory. As a result, the slave memory controller may map out the bad blocks with an address remapper by remapping good physical addresses of memory into linear logical addresses see FIG. While the address remapper may be programmable hardware, the address remapping functionality of translating logical addresses of data blocks into physical addresses of data blocks may occur in software at the operating system driver level instead of the SMC level.
Data is accessed in the 2D memory array row by row across the memory slices. The compound memory request may concurrently access data from each memory slice in the memory array row by row over different memory modules. A row of data may be formed including data responsive to the block memory requests Q, Q, and Q concurrently made by the compound memory request.
The data for each memory slice from each memory module may be packed together into a compound memory response and made available concurrently on the data bus to the master memory controller. For example, a compound memory response including packed memory slice responses may be formed in response to the compound memory request Assuming eight memory slices per memory module and memory rank, the compound memory response includes memory slice responses packed together, such as null data N for memory slice MS1, data D1 for memory slice MS2 responsive to a read access to memory location A1 , null data N for memory slice MS3, data D9 for memory slice MS4 responsive to a read access to memory location A9 , data D5 for memory slice MS5 responsive to a read access to memory location A5 , and null data N for memory slices MS6, MS7, and MS8.
The compound memory response may optionally include the same tag that was appended to the compound memory request When received, the tag may indicate to the master memory controller and the pending operations table that the given compound memory request into the two dimensional memory array is completed. In which case, the given entry into the pending operations table may be deleted. The row of data read out may be then transposed from rows into columns in the two-dimensional transposition buffer Data access by the processor with the transpositional buffer is column by column across rows of data stored therein.
In the case of a write operation, write data in the forms of blocks are transposed from columns into rows of data in the two-dimensional transposition buffer With the two-dimensional transposition buffer , a row of data may be concurrently written into the 2D memory array with a write compound memory request. That is, one processor may linearly access a column of storage locations in the transpositional buffer as shown in a first memory slice MS1.
From the point of view of the processor, each rank of memory in the 2D memory array appears to have a linear logical address space across the address space of the plurality of memory slices MS1-MSZ as illustrated in FIG. For example in a given rank of memory, the processor may seem to be sequentially addressing through the linear logical address space of the first memory slice, MS1, before jumping over to sequentially address through the linear logical address space of the second memory slice, MS2.
A write compound memory request may wait for the aggregation of a number of block memory requests before accessing the 2D memory array.
With write data stored in a sufficient number of storage locations in a row of the transpositional buffer , the write compound memory request may occur with a row of data being drained out of the transpositional buffer and written into the memory slices in the 2D memory array. From the point of view of the master memory controller, the 2D memory array appears to have a linear logical address space within each of the plurality of memory slices MS1-MSZ as illustrated in FIG.
Referring to FIG. In a typical compound memory request access into the 2D memory array, the same address e. The address is broadcast over each memory channel bus in the two-dimensional memory array.
Alternatively, different addresses may be used into each memory slice by one compound memory request e. In this case, the master memory controller initially issues a control-space write to the slave memory controllers in the 2D memory array to communicate the different addresses A, A90, A82, A80, etc.
The master memory controller can then issue a read or write respectively using a read from stored address command or a write into stored address command.
The data read from the two-dimension memory array is loaded row by row into the storage locations in the transpositional buffer That is, one processor may linearly access and read a column of storage locations in the transpositional buffer as shown in an Nth memory slice MSN. As shown and described, a single two-dimensional transposition buffer may be used to support compound memory requests—one or more block memory requests for data in memory slices of a given rank.
Each read compound memory request includes one or more read block memory requests to read a certain set of data blocks from memory.
Each write compound memory request includes one or more write block memory requests to write a certain set of data blocks into memory. However, a given compound memory request typically does not include a combination of read block memory requests and write block memory requests to maximize data bandwidth over a channel.
The master memory controller MMC has full control over the one or more memory channels to which it is coupled. The master memory controller's control over the one or more memory channels permits the same two-dimensional transposition buffer to be used for both read and write operations.
Read and write operations may overlap at the memory module level as well. Write data is moved from the master memory controller into staging areas in the slave memory controller, such as the shared memory , so that a read data operation may occur into memory. The process begins with a start process block and then goes to process block At process block , a plurality of block memory requests are received and stored in a buffer.
The process then goes to process block At process block , a plurality of block memory requests stored in the buffer are combined or aggregated together into a compound memory request. At process block , a determination is made if the compound memory request is a write request. This may be known in advance if a memory block read request buffer and a memory block write request buffer are provided. If a write request, the process goes to process block If it is not a write request e.
At process block , a determination is made if the compound memory request is a read request. If a read request, the process goes to block If neither a write request or a read request e. At block with the compound memory request being a write request, memory block data is transposed and aggregated together as a row of data over memory slices in each memory module in the 2D memory array.
The process then goes to block At process block , the aggregated data is concurrently written into a row over the memory slices in the 2D memory array. The process then goes back to process block to continue receiving and storing block memory requests into a buffer. At block , data within the memory of one or more memory modules is concurrently read and aggregated together as a memory module output response for each memory slice.
At block , the transpositional buffer is made ready to receive data in parallel for each memory slice in the memory array. Multi-chip packages may also be referred to as hybrid packages or multi-chip module packages.
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